1. Field of the Invention
This invention relates to a silicon carbide semiconductor device and to a manufacturing method thereof. A silicon carbide semiconductor device according to the invention can for example be used as an insulated gate type field effect transistor and particularly as a vertical type high-power MOSFET.
2. Description of the Related Art
As a silicon carbide semiconductor device in the related art, a trench gate type power MOSFET having low on-resistance and superior withstand voltage has been proposed (Japanese Patent Application Laid-Open No. H. 7-326755 or Japanese Patent Application Laid-Open No. H. 8-70124).
In this trench gate type power MOSFET, as shown in FIG. 39, a semiconductor substrate 4 is made up of an n.sup.+ -type monocrystalline silicon carbide (SiC) semiconductor substrate 1, an n.sup.- -type epitaxial layer 2 and a p-type epitaxial layer 3. This semiconductor substrate 4 consists of hexagonal system monocrystalline silicon carbide, and its upper face (principal face) is a substantially (0001) carbon face.
An n.sup.+ -type source region 5 is formed in a predetermined region of the surface of the p-type epitaxial layer 3, and a trench 7 is formed passing through a predetermined region of the n.sup.+ -type source region 5. This trench 7 passes through the p-type epitaxial layer 3 as well as the n.sup.+ -type source region 5, and reaches the n.sup.- -type epitaxial layer 2. The trench 7 has a side face 7a perpendicular to the surface of the p-type epitaxial layer 3 and a bottom face 7b parallel with the surface of the p-type epitaxial layer 3.
A gate insulating film (gate oxide film) 9 is formed in the trench 7. The inside of this gate oxide film 9 is filled with a gate electrode layer 10. An interlayer insulating film 11 is disposed on the gate electrode layer 10. On the surface of the n.sup.+ -type source region 5 including the interlayer insulating film 11 and on the surface of the p-type epitaxial layer 3 a source electrode layer 12 is further formed. This source electrode layer 12 is in contact with both the n.sup.+ -type source region 5 and the p-type epitaxial layer 3. Also, on the surface of the n.sup.+ -type silicon carbide semiconductor substrate 1 (the rear surface of the semiconductor substrate 4), a drain electrode layer 13 is formed.
When a positive voltage is impressed on the gate electrode layer 10, the surface of the p-type epitaxial layer 3 at the side face 7a of the trench 7 becomes a channel and a current flows between the source electrode layer 12 and the drain electrode layer 13 through the channel.
The source-drain withstand voltage in the trench gate type power MOSFET described above is determined by the condition at which avalanche breakdown of the pn junction between the p-type epitaxial layer 3 and the n.sup.- -type epitaxial layer 2 occurs and the condition at which the p-type epitaxial layer 3 is depleted throughout so that punch-through arises. Since the withstand voltage with respect to punch-through changes with variation in the film thickness of the p-type epitaxial layer, setting it to a predetermined withstand voltage is difficult. Because of this, it is necessary while making the voltage at which avalanche breakdown occurs high to also make sure that avalanche breakdown occurs before punch-through in order to set the withstand voltage to a desired value. To prevent punch-through and also make the voltage at which avalanche breakdown occurs high it is necessary to make the impurity concentration of the p-type epitaxial layer 3 amply high and make the thickness "a" of the region sandwiched between the n.sup.+ -type source region 5 and the n.sup.- -type epitaxial layer 2 amply thick.
However, when the impurity concentration of the p-type epitaxial layer 3 is made high, the gate threshold voltage becomes high, and because the channel mobility falls due to increase in impurity scattering, the on-resistance increases. There is also the problem that when the thickness "a" becomes large, the channel length becomes long and a channel resistance and the on-resistance increase.
To overcome those problems, the present applicant has proposed a semiconductor device wherein as shown in FIG. 40 at the side face 7a of the trench 7 an n-type thin film semiconductor layer 8 of silicon carbide is formed by epitaxial growth on the surfaces of the n.sup.+ -type source region 5, the p-type epitaxial layer 3 and the n.sup.- -type epitaxial layer 2 (Japanese Patent Application Laid-Open No. H. 9-74191).
In this semiconductor device shown in FIG. 40, by using the n-type thin film semiconductor layer 8 as a channel-forming region and applying an electric field to the gate oxide film 9 by impressing a voltage on the gate electrode layer 10, an accumulation-type channel is induced in the n-type thin film semiconductor layer 8 and a current is made to flow between the source electrode layer 12 and the drain electrode layer 13 through the accumulation-type channel.
By thus making the MOSFET operate by means of an accumulation-type channel induced without inverting the conductive type of the channel-forming region, compared to an inverted-type channel MOSFET wherein the conductive type of the channel-forming region is inverted to induce the channel, it is possible to make the MOSFET operate with a low gate voltage.
Also, according to the structure as shown in FIG. 40, it is possible to control independently the impurity concentration of the p-type epitaxial layer 3 and the impurity concentration of the n-type thin film semiconductor layer 8 where the channel is formed. Therefore, it is possible to make the impurity concentration of the p-type epitaxial layer 3 high and to shorten the channel length by making the thickness "a" sandwiched between the n.sup.+ -type source region 5 and the n.sup.- -type epitaxial layer 2 small, and it is thereby possible to obtain a high withstand voltage and also make the on-resistance low.
Also, by making low the impurity concentration of the n-type thin film semiconductor layer 8 in which the channel is formed it is possible to reduce the influence of impurity scattering when carriers flow. As a result, the channel mobility can be made large and it is possible to make the on-resistance small and make power losses small.
Therefore, with the trench gate type power MOSFET shown in FIG. 40 it is possible to obtain a silicon carbide semiconductor device having a high withstand voltage and low power loss.